[Patent Literature 1] JP 2005-192192 A
[Patent Literature 2] JP 2014-033428 A (WO 2014/010236 A1)
[Nonpatent Literature 1] PCI Express Architecture PCI Express Jitter and BER Revision 1.0, 11 Feb. 2005
[Nonpatent Literature 2] Serial ATA: High Speed Serialized AT Attachment Revision 1.0a, 7 Jan. 2003
[Nonpatent Literature 3] Universal Serial Bus Specification Revision 2.027 Apr. 2000
[Nonpatent Literature 4] Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems Richard C. Walker, 2003
[Nonpatent Literature 5] Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling, J. Kim, IEEE Communications Magazine, December 2003, p. 68-74
A technology of clock data recovery (CDR) in data communications is required to provide a short lock time when the data are intermittently transmitted (when starts and stops of transmission are repeated). For example, PCI Express adopts CDR with phase interpolator, in order to realize a short lock time (refer to Nonpatent Literature 1). In the CDR with phase interpolator, a receiver generates a plurality of clocks having different phases and selects one of the clocks that has a phase closest to that of the received data. This CDR with phase interpolator has a function to select a clock but no function to adjust a clock frequency. This requires a clock frequency error (offset) to be small between a clock source (i.e., an oscillation source) of a data transmission side and a clock source of a data reception side. For instance, Nonpatent Literature 1 uses an identical clock source in both the data transmission side and the data reception side so as not to produce a clock frequency error.
Moreover, Serial ATA requires a clock source in a data reception side to have a clock frequency error of ±350 [ppm] whereas requiring a clock source in a data transmission side to have a clock frequency error similar to that of the data reception side. Thereby, the clock frequency error can be small between the clock sources in the data transmission side and the data reception side, so that a short lock time is achieved (refer to Nonpatent Literature 2).
Furthermore, USB specifies that a synchronous pattern having a small bit length is used to lock on the premise that the clock frequency error is small enough in between the clock sources of the data transmission side and the data reception side. To be specific, in Nonpatent Literature 3, the dock frequency error needs to be 0.25% (=0.21 [nsec]/( 1/12 [Mbps]).
Further, the transmission of video signals uses data communications that transmit data continuously. In such communications, data can be transmitted continuously once the lock is fulfilled. Thus, even if a lock time is long, CDR with phase synchronization is adopted (refer to Nonpatent Literature 4). Suppose that the phase comparison needs 500 cycles, for instance. The phase comparison requires the change points of bits while the presence probability of the change points of bits is about 50%. The lock thus needs about 1000 bits. In particular, the clock frequency error as well as the phase error arises at the time when the power is turned on. The lock further needs additional bits so that the necessary number of bits becomes 10,000 bits, for instance. This requires the lock time in CDR with phase synchronization to be shorter as much as possible. For instance, another technology is disclosed which oversamples a bit string of data and conducts signal processing with a digital circuit (refer to Nonpatent Literature 5 and Patent Literature 1).
The Inventors found the following. As indicated in Nonpatent Literatures 1, 2, and 3, the CDR with phase interpolator is supposed to use clock sources each having a small clock frequency error between a data transmission side and a data reception side for realizing a short lock time. However, a CR oscillation circuit, which functions as a clock source built in LSI (Large Scale Integration), generally provides a clock frequency error of about 10%. Thus, another clock source such as a crystal oscillator having a small frequency error needs to be provided as an independent body to be separate from an LSI.
Further, as indicated in Nonpatent Literature 4, the CDR with phase synchronization needs a long lock time that is unsuitable for data communications. Furthermore, oversampling each bit of data and subsequent digital processing can shorten a lock time to some extent; however, the effect may be limited. That is, Nonpatent Literature 5 and Patent Literature 1 provide only a technique to use a digital circuit for achieving a feedback loop of PLL (Phase-Locked Loop) realized in an analog circuit; thus, the technique finds a difficulty in shortening a lock time significantly. To be specific, in Nonpatent Literature 5, the number of loop filters for feedback is 512 or more, and the lock time thus needs the number of bits of multiples of 512. Moreover, Patent Literature 1 supposes a clock frequency error of about 1000 [ppm] on the premise that a clock frequency can be estimated when the phase is determined.
To that end, the Applicant filed Patent Literature 2 disclosing a data reproduction method by determining an identical-value bit length of a received bit string even with a configuration permitting a data receive-side clock source to have a degree of clock frequency error or difference from that of a data transmit-side clock source. That is, the method calculates an integrated number of bits by integrating the predetermined number of bits in a received bit string, and calculates an integrated number of samples by integrating the number of samples corresponding to each bit of the predetermined number of bits in oversampling data. The method further obtains a fitting line (i.e., approximated line) based on a plurality of points each of which indicates correspondence between the integrated number of bits and the integrated number of samples, and determines an identical-value bit length corresponding to a segment in which identical values continue after the integrated number of samples in the oversampling data based on the fitting line.
Further, the Inventors found the following. That is, there may be a case where a duty cycle of each bit in a received bit string deviates significantly. Such a case causes the above method to find a difficulty in obtaining a fitting line accurately and determining an identical-value bit length in the received bit string.